Biomedical signals: From neurons to custom processing hardware

6th of March 2013

Aula Polivalente 2

Escuela Politécnica Superior
Universidad San Pablo CEU
Madrid - Spain

How to get here

Please confirm attendance emailing to gabriel.caffarenafernandez at ceu.es


AGENDA

12:000-12:25
"Trends on FPGA devices"
Ricardo Gómez-Galarza, Silica AVNET
 
12:25-12:40
Coffee
 
12:40-13:20
"Recording from the Brain: Present Technologies Applications and Limitations" [slides] [abstract]
C. Pedreira, University of Leicester, UK
 
  1. Overview of brain recording techniques
  2. DSP for brain signals interpretation
  3. Future challenges
 
13:20-14:00
"Program-to-hardware transformation and its use in heterogenous high-performance DSP" [slides] [abstract]
Madhav P. Desai, Indian Institute of Techology - Bombay, India
 
  1. Hardware compilation
  2. Extraction of parallelism
  3. Application to common DSP kernels

Speakers

C. Pedreira

Carlos Pedreira obtained his degree in Telecommunication Engineering from the Polytechnic University of Madrid in 2005. He worked for two years as an electronic engineer in the Aerospace Division of SENER ingenieria y sistemas. In 2006 Carlos started his post-graduates studies in the University of Leicester (United Kingdom), receiving his PhD in Neuroscience in 2010. Since then he is a Medical Research Council (MRC) Post-doctoral Fellow in the recently created Centre for Systems Neuroscience of the University of Leicester. Since 2011 he is a visiting Post-Doctoral researcher in the California Institute of Technology (Caltech). Carlos' research interests include the understanding of how episodic memories are linked to conscious perception, brain machine interfaces and the neural plasticity involving both processes.

Madhav P. Desai

Madhav P. Desai is currently a professor in the department of Electrical Engineering at the Indian Institute of Technology in Mumbai (IIT-Bombay), India. He received a B.Tech. (Electrical Engg.) from IIT-Bombay in 1984, and his M.S. and Ph.D. degrees in Electrical Engg. from the University of Illinois at Urbana-Champaign in 1986 and 1991 respectively. From January 1992 until June 1996, he was with the Semiconductor Engineering Group at the Digital Equipment Corporation (Hudson MA, USA). He joined IIT-Bombay in July 1996. His research activities have ranged from circuit simulation, interconnect modeling, the study of stochastic algorithms, FPGA systems for simulation acceleration, VLSI system architecture exploration and modeling and of course the problem mapping high-level programs to hardware. He has had extensive contact with Industry. During his tenure at Digital, he participated in the design of one of the earliest high performance microprocessors, the DEC 21064. Several of his research contributions have been accepted and widely used in industry: a 3D capacitance extractor (Intel), high speed packet classi_cation engines (Switch-On Networks), FPGA based simulation accelerator (Powailabs).


This is a free seminar. Please confirm attendance emailing to gabriel.caffarenafernandez at ceu.es