EURASIP Seminar

“Hardware Design os DSP Systems”

5 May 2010

Escuela Politécnica Superior

Sala Polivalente 1

Universidad San Pablo – CEU

Madrid, SPAIN

Programa:

	SESION I
10:30-12:15	*“DSP Design with FPGAs”* Xilinx System Generator
	Gabriel Cutillas Silica AVNET
12:15-12:30	Coffe break
	SESSION II
12:30-13:15	*“Design of 4G MIMO receiver”*
	Ángel Fernández Herrero Universidad Politécnica de Madrid
13:15-14:00	*"Design of Telecommunications VLSI systems "*
	Fernando Barbero SIDSA

Seminar sponsored by:

European Association for Signal Processing – www.eurasip.org

Universidad de San Pablo CEU – www.uspceu.es – www.eps.uspceu.es